module regCC (
    /*AUTOARG*/
   // Outputs
   e_cc,
   // Inputs
   clock, reset, e_alucc, e_setcc
   );

input           clock;
input           reset;
input   [2:0]   e_alucc; 
input           e_setcc;
output  [2:0]   e_cc;

/*AUTOREG*/
// Beginning of automatic regs (for this module's undeclared outputs)
reg [2:0]               e_cc;
// End of automatics
always @(posedge clock, posedge reset) begin
    if(reset) begin
        e_cc <= 3'b100;
    end else if(e_setcc) begin
        e_cc <= e_alucc;
    end
end

endmodule

